1. Field of the Invention
The present invention relates to a memory module, and more particularly to a memory module having a register.
2. Description of the Related Art
Generally, a memory module has a plurality of memory devices, and a plurality of memory modules are used as a main memory in computers. In order for a central processing unit (CPU) or a memory controller to directly provide a command/address signal to all of the memory devices, the CPU or the memory controller needs to have a high driving capability for driving the command/address signal. As the number of the memory devices receiving the command/address signal is increased, signal integrity can be degenerated so that the number of the memory devices is required to be reduced.
Thus, a memory module including a plurality of memory devices and a register, which provides a command/address signal to the plurality of memory devices, are used in a computer. The CPU or the memory controller provides the command/address signal to the register included in the memory module, instead of directly to all of the memory devices. Accordingly, in case of the computer including the plurality of memory modules, the CPU or the memory controller provides the command/address signal to only the register in each memory module instead of directly to all of the memory devices.
The memory module having the register generally uses an odd number of memory devices or an odd number of pairs of memory devices. Generally, in the memory module having the register, the register is arranged at the central part of the memory module to minimize a delay amount of the command/address signal. In other words, the memory devices are divided into two groups and the register, hereinafter referred to as a 1:2 register, has a 1:2 configuration. That is, one input terminal and two output terminals are used to provide the command/address signal to each of the groups of memory devices. If the number of the memory devices corresponds to an odd number, numbers of the memory devices included in the two memory groups can be different from each other. For example, in the case where the memory module includes nine memory devices, a first memory group can include five memory devices and a second memory group can include four memory devices. Accordingly, the command/address signal provided to the first memory group cannot be synchronized with the command/address signal provided to the second memory group. Such a mismatch can be insignificant in the memory module that operates at low speed, but can cause trouble in the memory module that operates at high speed.
FIG. 1 is a block diagram illustrating a conventional memory module having a register. Referring to FIG. 1, a memory module 100 includes nine memory devices 121 through 129 and a register 110.
The register 110 receives a command/address signal through a command/address signal input line 101 from the exterior of the memory module 100. The register 110 provides the command/address signal to a first memory group through a first signal line 131 and a first node Na, and provides the command/address signal to a second memory group through a second signal line 132 and a second node Nb. The first memory group includes five memory devices 121, 122, 123, 124 and 125, and the second memory group includes four memory devices 126, 127, 128 and 129.
The number of memory devices coupled to the first signal line 131 is larger than the number of memory devices coupled to the second signal line 132, so that a delay amount of the first signal line 131 is larger than a delay amount of the second signal line 132, that is, a mismatch is caused.
In order to reduce the mismatch, a length L1 of the first signal line 131 can be shorter than a length L2 of the second signal line 132. In order words, the first signal line 131 can be arranged with the shortest routing path from the register 110 to the first node Na, and the second signal line 132 can be arranged with a longer routing path with respect to the first signal line 131.
FIG. 2 is a block diagram illustrating a 1:2 register included in the memory module in FIG. 1. Referring to FIG. 2, a 1:2 register 200 includes a clock buffer 210, an input buffer 220, a D-type flip-flop 230, and first and second output buffers 240 and 241. The clock buffer 210 is provided with an external clock signal CLK. The input buffer 220 is provided with a command/address signal ADDIN from the exterior. The D-type flip-flop 230 outputs the command/address signal in synchronization with the clock signal outputted from the clock buffer 210. The first and second output buffers 240 and 241 buffer the command/address signal outputted from the D-type flip-flop 230. The first output buffer 240 provides the command/address signal to the first memory group, and the second output buffer 241 provides the command/address signal to the second memory group.
Accordingly, signal integrity can be improved by the register in the memory module, and the mismatch can be minimized by lengthening the routing path of the second signal line. However, a lengthened routing path of the second signal line can result in an increase of an area of the memory module. For example, in case that the command/address signal corresponds to a 20-bit signal and the routing path of the command/address signal transfers the 20-bit signal in parallel, the area of the memory module can be increased in proportion to the length of the routing path. Furthermore, when the routing path of the signal line is lengthened, interference between signals can be increased.
Therefore, the routing path of the signal line in a memory module is needed to be minimized.